1. Technical Field
This invention generally relates to integrated circuits. More specifically, the present invention relates to enhancing the performance of Silicon On Insulator (501) devices.
2. Background Art
Today, our society is heavily dependent on high-tech electronic devices for everyday activity. Integrated circuits are the components that give life to our electronic devices. Integrated circuits are found in widespread use throughout our country, in appliances, in televisions and personal computers, and even in automobiles. Additionally, manufacturing and production facilities are becoming increasingly dependant on the use of integrated circuits for operational and production efficiencies. Indeed, in many ways, our everyday life could not function as it does without integrated circuits. These integrated circuits are manufactured in huge quantities in our country and abroad. Improved integrated circuit manufacturing processes have led to drastic price reductions for these devices.
The traditional integrated circuits fabrication process is a series of steps by which a geometric pattern or set of geometric patterns is transformed into an operating integrated circuit. An integrated circuit consists of superimposed layers of conducting, insulating, and transistor-forming materials. By arranging predetermined geometric shapes in each of these layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process typically consists of the patterning of a particular sequence of successive layers using various chemicals as etchants. Many different processes exist for creating a pattern on the silicon wafer, with different processes being specifically adapted to produce the desired type of integrated circuit.
One relatively new process for fabricating integrated circuit devices is commonly known as Silicon On Insulator (SOI). SOI devices are semiconductor devices which are formed within a thin silicon layer that overlies an electrically insulating region formed over an integrated circuit substrate material. This insulating region may include, for example, a layer of SiO2, deposited over a semiconductor substrate material such as silicon or gallium arsenide. This fabrication process allows devices to be created which are electrically isolated from the substrate. SOI devices offer several advantages over conventional semiconductor devices.
For example, SOI devices typically have lower parasitic capacitances which, in turn, translate into faster switching times for the resulting circuits. In addition, the well-known but undesirable phenomenon of “latchup,” which is often exhibited by conventional Complementary Metal-Oxide Semiconductor (CMOS) devices, is avoided when CMOS devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may shorten the life of traditional integrated circuits.
The advantageous characteristics of SOI devices result from the dielectric isolation described above. While providing many advantages, this dielectric isolation also produces some difficulties not encountered with more conventional integrated circuit devices. In conventional devices, electrical interactions occur between the device substrate and the device active region, e.g. the current-carrying portion of the device, such as the current channel of a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET). Occasionally, accumulated charge in the device active region can alter the device threshold voltage VT (i.e., the voltage at which the current channel of an enhancement-mode MOSPET begins to conduct current). However, in conventional devices, this accumulated charge is readily removed through the substrate by applying an appropriate voltage to the substrate which attracts the accumulated charge away from the active layer, into the substrate, and out through a conductive lead. For example, a negative voltage applied to the substrate attracts holes from the active layer into the substrate, while a positive voltage attracts electrons. Alternatively, it is possible to change the threshold voltage of a conventional integrated circuit device, if desired, by applying a voltage to the active, region through the electrically connected substrate. This is known as the “body effect.”
In contrast, in a typical SOI device, the insulating region prevents both the conduction of charge from the active region into the substrate and the application of a voltage to the active region through the substrate. Thus, the lack of flexibility in the operation of an integrated circuit device due to the SOI insulating region is often inconvenient. For example, during operation of a typical SOI MOSFET, electrical charge can accumulate in the body of the device, (the region of the MOSFET between the source and the drain), until the concomitant electrical potential increases sufficiently to produce a shift in the threshold voltage (VT) of the device. This shift can adversely affect the operation of the circuit and introduce errors into the information being processed by the device. The charge accumulates on the body of the SOI transistors in a circuit whenever the circuit is not being supplied with voltage.
For example, in a typical circuit using bulk CMOS devices, the body of an n-FET device will be connected to ground and the body of a p-FET device will be connected to the supply voltage (VDD). Therefore, even when no voltage is applied to the n-FET or the p-FET, the body potential is controlled by the connection to either ground or VDD and the operational VT will be in keeping with standard design parameters for each device. In contrast, the body of an SOI device is not connected to either ground or VDD and, therefore, the body of the device can “float” to any voltage level. In addition, thermal fluctuations can also cause electrical charges to accumulate in the body of the transistors. Over a period of time, this charge can accumulate and can cause VT to be lower than the specified design parameters and the transistor will switch on before it should. If VT has been altered significantly, the operation of the circuit can be effected. For example, in synchronization circuits with critical timing requirements, the transistor may not switch on at the appropriate time and the circuit may not operate at all.
One specific example of the problems associated with SOI integrated devices is illustrated in FIG. 4. In FIG. 4, a typical memory circuit 400 with 256 local word line drivers comprises a highest order local word line (LWL255) circuit 430 which includes transistor 432 and node 431; a lowest order local word line circuit (LWL0) 440; a segment driver 450 which includes a pass transistor 451; and a select line 460. The illustrated circuit represents a small portion (one segment) of a much larger memory array on a typical memory chip. The lowest order local word line (LWL0) circuit 440 is driven by a low order Global Word Line (GLW0). The highest order local word line (LWL255) circuit 430 is, correspondingly, driven by a high order Global Word Line 255 (GWL255). The intervening word lines (not shown) are likewise driven by other global word lines (not shown).
The individual segments in a memory array are accessed by activating segment driver 450. When memory circuit 400 is not being accessed, all of the global word lines are deselected and are at a low voltage level and, due to the operation of the transistors connected to GWL255 shown in circuit 430, node 431 is connected to VDD. All of the remaining word lines circuits (GWL0-GWL254) operate in the same way. When segment driver 450 is not selected, transistor 432, and the corresponding transistors in the other local word driver circuits, are not driven and are therefore turned off. Circuit 435 represents the load of the remaining word line drivers. Due to the accumulated charge stored on each of the transistors represented by this load, select line 460 appears to circuit 400 as if it were a large capacitor with a stored charge.
When segment driver 450 is activated, one of the active global word lines will provide access to a local word line for reading or writing to a specific memory location. This process is accomplished as follows. The memory chip is activated by supplying-a signal to the CLOCK input of segment driver 450. The control (CTL) or segment signal is used to select one of the memory subarrays or segments for reading or writing. After a small propagation delay, the control circuit (not shown) creates a decoding signal DECODE that activates the appropriate subarray by driving select line 460 to low. When all three of the input signals to segment driver 450 are active, node 431 in the local word line driver circuit 430 is discharged through select line 460 and pull-down transistor 451 in segment driver 450.
At this point, although only one of the 256 global word lines is selected, segment driver 450 must discharge all of the accumulated charge in the body of each transistor corresponding to transistor 432 in local word line driver 430 for each of the 256 local word line drivers. This is known as “fan-out” loading. As described earlier, the bodies of the SOI transistors have a tendency to accumulate electrical charge. When a given memory segment is not being accessed for a period of time (i.e. 0.1 ms for a typical n-FET device), an electrical charge can accumulate in the body of each one of the SOI transistors. Then, when the memory segment is first accessed, the charge on each of the transistors corresponding to transistor 432 must be discharged. The “first access” is considered to be when the segment is first used to read or write data after a period of inactivity. If subsequent accesses are to the same memory segment, no charge sufficient to cause delays will have been accumulated. If, however, a different memory segment is subsequently accessed, the previously accessed memory segment may, once again, need to be discharged prior to subsequent accesses. Memory access is delayed until the electrical charge is dissipated.
The fan-out loading effect is known for a tendency to slow down memory 25 access times associated with SOI devices, especially during the first cycle of operation, when the accumulated charge on the body of the transistors is the greatest. Also, the greater the physical distance between segment driver 450 and the selected local word line driver, the harder it is to drive. Due to the propagation delay inherent in the physical circuit wiring, body charges in more distant devices take longer to discharge through the long, relatively resistive wire. However, after the first access cycle, the SOI loading effect is diminished significantly. This is because, once the accumulated body charges in all of the N-channel FET pull-down devices have been discharged, a relatively long period of time is needed to build up the charge on the body of the transistors again. Therefore, as long as the memory access requests are to the same subarray or segment, there will be no additional access delay associated with discharge propagation delays. By logical extension, the worst access times for an SOI memory device is generally the first access cycle for a device that is located the farthest distance from segment driver 450.
The loading effect described above can be completely eliminated by connecting the body of an SOI device to a reference ground. Referring now to FIG. 7, a SOI transistor 700 formed with a body contact for connecting the body of transistor 700 to ground is shown. SOI transistor 700 has a body implant mask region 710, a source/drain implant mask region 720, a T-shaped gate 725; a source contact 730, a drain contact 740, and a body contact 750. Body contact 750 is typically connected to ground for an n-channel device and to VDD for a channel device. The creation of body contact 750 requires additional processing and mask steps when transistor 700 is being fabricated. If body contact 750 is connected to ground, the problems associated with charge build-up on the body of transistor 700 are eliminated. However, this will also negatively impact circuit operation in at least two ways. First, circuit overhead (i.e. the amount of area needed to fabricate the circuit) is significantly increased and, second, the speed advantage inherent in SOI circuits is also eliminated, because the lower variable VT of SOI devices is not longer present.
Therefore, there exists a need to provide a way to rake advantage of the benefits of SOI device characteristics without suffering the possible negative implications of SOI fabricated devices. In addition, the methods employed should not unnecessarily diminish or destroy the positive advantages provided by implementing circuits and devices using SOI technology.